CWE-515 Covert Storage Channel
baseA covert storage channel transfers information through the setting of bits by one program and the reading of those bits by another. What distinguishes this case from that of ordinary operation is that the bits are used to convey encoded information.
01
parent weaknesses
Broader classes this is a kind of.
02
vulnerabilities (6)
Known CVEs related to this entry.
| ID | severity | exploitable | ||
|---|---|---|---|---|
| CVE-2026-54316US | critical9.1 | Exploit | ||
Claude Code is an agentic coding tool. From 0.2.54 until 2.1.163, because the hostname huggingface.co was pre-approved as a bare hostname for the WebFetch tool, any path on that d… | ||||
| CVE-2018-12126US | medium5.6 | — | ||
Microarchitectural Store Buffer Data Sampling (MSBDS): Store buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable i… | ||||
| CVE-2026-43261US | medium5.5 | — | ||
In the Linux kernel, the following vulnerability has been resolved:
arm64: Add support for TSV110 Spectre-BHB mitigation
The TSV110 processor is vulnerable to the Spectre-BHB (Br… | ||||
| CVE-2026-31781US | medium5.5 | — | ||
In the Linux kernel, the following vulnerability has been resolved:
drm/ioc32: stop speculation on the drm_compat_ioctl path
The drm compat ioctl path takes a user controlled poi… | ||||
| CVE-2019-11091US | medium5.6 | — | ||
Microarchitectural Data Sampling Uncacheable Memory (MDSUM): Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potential… | ||||
| CVE-2019-0117US | medium4.4 | — | ||
Insufficient access control in protected memory subsystem for Intel(R) SGX for 6th, 7th, 8th, 9th Generation Intel(R) Core(TM) Processor Families; Intel(R) Xeon(R) Processor E3-150… | ||||
03
source
Where this definition is published.
MITREUS
scry
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