CWE-1342 Information Exposure through Microarchitectural State after Transient Execution
baseThe processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.
01
parent weaknesses
Broader classes this is a kind of.
02
vulnerabilities (3)
Known CVEs related to this entry.
| ID | severity | exploitable | ||
|---|---|---|---|---|
| CVE-2022-40982US | medium6.5 | — | ||
Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R) Processors may allow an authenticated user to po… | ||||
| CVE-2026-18796US | — | — | ||
Any application that
uses external QSPI flash for encrypted XIP on nRF5340 and relies on that
encryption for confidentiality and/or integrity of the externally stored… | ||||
| CVE-2023-28746US | — | — | ||
Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to pot… | ||||
03
attack patterns (1)
CAPEC attack patterns that exploit this.
04
source
Where this definition is published.
MITREUS
scry
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