CVE-2026-29642
highpriority · track · 0EPSS 0.001 · 1 %ileEUEPSS · scored 2026-10-27
A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as "writes preserve values, reads ignore values," i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.
cvss
Technical severity, 0–10. One row per scoring source.
base score 0–10 · higher = more severe · hover a vector to decode
ssvc
A stakeholder decision — act, attend, or track — from exploitation and impact.
weaknesses
The CWE weakness classes this flaw belongs to.
affected products (1)
Products and version ranges known to be affected.
also known as (3)
Other names and identifiers for this entity.
sources
Which sources assert this record, and when.
references (11)
External citations — patches, advisories, analysis.
- https://access.redhat.com/security/cve/cve-2026-29642cnnvd
- https://github.com/OpenXiangShan/XiangShan/tagsPatchcnnvd
- https://nvd.nist.gov/vuln/detail/CVE-2026-29642cnnvd
- https://docs.riscv.org/reference/isa/priv/machine.htmlenisa_euvd
- https://docs.riscv.org/reference/isa/priv/priv-csrs.htmlenisa_euvd
- https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63enisa_euvd
- https://github.com/OpenXiangShan/XiangShan/issues/3934enisa_euvd
- https://docs.riscv.org/reference/isa/priv/machine.htmlnvd
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