CVE-2026-20760
mediumpriority · track · 0EPSS 0.001 · 1 %ileDEEUEPSS · scored 2026-10-27
Improper handling of overlap between protected memory ranges in some microcode for some Intel(R) Processors within Ring 0: Hypervisor may allow an escalation of privilege. Authorized adversary with a privileged user combined with a low complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are not present without special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (high) and availability (high) of the vulnerable system, resulting in subsequent system confidentiality (none), integrity (none) and availability (none) impacts.
cvss
Technical severity, 0–10. One row per scoring source.
base score 0–10 · higher = more severe · hover a vector to decode
ssvc
A stakeholder decision — act, attend, or track — from exploitation and impact.
weaknesses
The CWE weakness classes this flaw belongs to.
affected products (17)
Products and version ranges known to be affected.
- Intel Prozessor Core Ultra Processorsall versionscert_bundDEcpe:/h:intel:intel_prozessor:core_ultra_processors
advisories (1)
Vendor and ecosystem advisories describing this.
- WID-SEC-W-2026-2772Intel Prozessor: Mehrere SchwachstellenDeutsch2026-08-11csaf · cert_bundDE
Ein lokaler Angreifer kann mehrere Schwachstellen in Intel Prozessor ausnutzen, um erweiterte Rechte zu erlangen, Daten zu manipulieren, vertrauliche Informationen offenzulegen oder einen Denial-of-Service-Zustand auszulösen.
also known as (3)
Other names and identifiers for this entity.
sources
Which sources assert this record, and when.
references (3)
External citations — patches, advisories, analysis.
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