CVE-2021-28692

mediumpriority · track · 28EPSS 0.003 · 21 %ileEURUUS
grimoire priorityP3 · Track
Exploitable?
—
no known exploitation
Likely / severe?
0.29% (21st) EPSS
CVSS 5.6 · medium
Is it mine?
14 products
Check your exposure
Who says so?
4 sources
cnnvd · enisa_euvd · fstec_bdu · nvd

EPSS · scored 2026-10-27

inappropriate x86 IOMMU timeout detection / handling IOMMUs process commands issued to them in parallel with the operation of the CPU(s) issuing such commands. In the current implementation in Xen, asynchronous notification of the completion of such commands is not used. Instead, the issuing CPU spin-waits for the completion of the most recently issued command(s). Some of these waiting loops try to apply a timeout to fail overly-slow commands. The course of action upon a perceived timeout actually being detected is inappropriate: - on Intel hardware guests which did not originally cause the timeout may be marked as crashed, - on AMD hardware higher layer callers would not be notified of the issue, making them continue as if the IOMMU operation succeeded.

01

cvss

Technical severity, 0–10. One row per scoring source.

7.1
010

base score 0–10 · higher = more severe · hover a vector to decode⚠ sources disagree · medium–high · 5.6–7.1

v2.05.6mediumAV:L/AC:L/Au:N/C:P/I:N/A:Cprimary · NVD / NIST USexploitability 3.9 · impact 7.8
v3.17.1highCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:Hprimary · NVD / NIST USexploitability 1.8 · impact 5.2
v3.17.1highAV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:Hsecondary · FSTEC (BDU) RU
v3.16.5mediumCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:H/E:Usecondary · CVSS-BT (t0sche)
02

weaknesses

The CWE weakness classes this flaw belongs to.

03

affected products (14)

Products and version ranges known to be affected.

04

also known as (4)

Other names and identifiers for this entity.

05

sources

Which sources assert this record, and when.

published 2021-06-30modified 2026-06-17
07

references (17)

External citations — patches, advisories, analysis.

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